Stanford engineers find a simple yet clever way to boost chip speeds
Inside each chip are millions of tiny wires to transport data; wrapping them in a protective layer of graphene could boost speeds by 30 percent.
A typical computer chip includes millions of transistors connected with an extensive network of copper wires. Although chip wires are unimaginably short and thin compared with household wires, both have one thing in common: in each case the copper is wrapped within a protective sheath.
For years a material called tantalum nitride has formed a protective layer around chip wires.
Now Stanford-led experiments demonstrate that a different sheathing material, graphene, can help electrons scoot through tiny copper wires in chips more quickly.
Graphene is a single layer of carbon atoms arranged in a strong yet thin lattice. Stanford electrical engineer H.-S. Philip Wong says this modest fix, using graphene to wrap wires, could allow transistors to exchange data faster than is currently possible. And the advantages of using graphene could become greater in the future as transistors continue to shrink.
“Researchers have made tremendous advances on all of the other components in chips, but recently there hasn’t been much progress on improving the performance of the wires,” he said.
Wong, the Willard R. and Inez Kerr Bell Professor in the School of Engineering, led a team of six researchers, including two from the University of Wisconsin-Madison, who will present their findings at the Symposia of VLSI Technology and Circuits in Kyoto, Japan, a leading venue for the electronics industry.
Ling Li, a graduate student in electrical engineering at Stanford and first author of the research paper, explained why changing the exterior wrapper on connecting wires can have such a big impact on chip performance.
Stanford researchers have demonstrated that sheathing semiconductor wires in graphene can help electrons scoot through tiny copper wires in chips more quickly. (Photo: nobeastsofierce/iStock)
It begins with understanding the dual role of this protective layer: it isolates the copper from the silicon on the chip and also serves to conduct electricity.
On silicon chips, the transistors act like tiny gates to switch electrons on or off. That switching function is how transistors process data.
The copper wires between the transistors transport this data once it is processed.
The isolating material – currently tantalum nitride – keeps the copper from migrating into the silicon transistors and rendering them non-functional.
Why switch to graphene?
Two reasons, starting with the ceaseless desire to keep making electronic components smaller.
When the Stanford team used the thinnest possible layer of tantalum nitride needed to perform this isolating function, they found that the industry-standard was eight times thicker than the graphene layer that did the same work.
Graphene had a second advantage as a protective sheathing, and here it’s important to differentiate how this outer layer functions in chip wires compared with household wires.
In house wires, the outer layer insulates the copper to prevent electrocution or fires.
In a chip, the layer around the wires is a barrier to prevent copper atoms from infiltrating the silicon. Were that to happen, the transistors would cease to function. So the protective layer isolates the copper from the silicon
The Stanford experiment showed that graphene could perform this isolating role while also serving as an auxiliary conductor of electrons. Its lattice structure allows electrons to leap from carbon atom to carbon atom straight down the wire, while effectively containing the copper atoms within the copper wire.
These benefits – the thinness of the graphene layer and its dual role as isolator and auxiliary conductor – allow this new wire technology to carry more data between transistors, speeding overall chip performance in the process.
In today’s chips the benefits are modest; a graphene isolator would boost wire speeds from 4 percent to 17 percent, depending on the length of the wire.
But as transistors and wires continue to shrink in size, the benefits of the ultrathin yet conductive graphene isolator become greater. The Stanford engineers estimate that their technology could increase wire speeds by 30 percent in the next two generations
The Stanford researchers think the promise of faster computing will induce other researchers to get interested in wires, and help to overcome some of the hurdles needed to take this proof of principle into common practice.
This would include techniques to grow graphene, especially growing it directly onto wires while chips are being mass-produced. In addition to his University of Wisconsin collaborator Professor Michael Arnold, Wong cited Purdue University Professor Zhihong Chen. Wong noted that the idea of using graphene as an isolator was inspired by Cornell University Professor Paul McEuen and his pioneering research on the basic properties of this marvelous material. Alexander Balandin of the University of California-Riverside has also made contributions to using graphene in chips.
“Graphene has been promised to benefit the electronics industry for a long time, and using it as a copper barrier is perhaps the first realization of this promise,” Wong said.
The Stanford-led experiments were sponsored in part by STARnet FAME Center, the National Science Foundation and the Stanford Initiative for Nanoscale Materials and Processes.
Tom Abate, Associate Director of Communications, Stanford Engineering, firstname.lastname@example.org, 650-736-2245
Last modified Wed, 17 Jun, 2015 at 12:20