Mark Horowitz
Professor Horowitz’s initial work focused on designing high-performance digital systems by combining work in computer-aided design tools, circuit design, and system architecture. Dr. Horowitz's current research interests are quite broad and span using EE and CS analysis methods to problems in molecular biology to creating new design methodologies for analog and digital VLSI circuits. He has worked on many processor designs, from early RISC chips, to creating some of the first distributed shared memory multiprocessors, and is currently working on on-chip multiprocessor designs. Recently he has worked on a number of problems in computational photography. In 1990, he took leave from Stanford to help start Rambus Inc., a company designing high-bandwidth memory interface technology, and has continued work in high-speed I/O at Stanford. His current research includes updating both analog and digital design methods, low energy multiprocessor designs, computational photography, and applying engineering to biology.
Last modified Tue, 2 Oct, 2012 at 11:28
| Title | Author(s) | Journal | Date |
|---|---|---|---|
| The implementation of a 2-core, multi-threaded itanium family processor | Horowitz, MA, et. al. | IEEE Journal of Solid-State Circuits | 01-2006 |
| False coupling exploration in timing analysis | Horowitz, MA, et. al. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 11-2005 |
| A 20-Gb/s 0.13- mu m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer | Horowitz, MA, et. al. | IEEE Journal of Solid-State Circuits | 04-2005 |
2010 SIA Faculty Researcher Award
2009 International Symposium of Computer Arch, Most influential paper in the 1994 conference.
2006 IEEE Donald O. Pederson Technical Field Award
2005 ISQED Best Paper Award
2004 International Symposium on Computer Architecture, Most Influential Paper from 1989
2003 Jack Kilby Outstanding Paper Award, ISSCC
Elected Fellow, Association for Computing Machinery
Elected Fellow, IEEE