Yoshio Nishi

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Nishi's research interest has been in silicon and germanium-based CMOS devices, processes and materials. He is currently interested in research for new device structures with new materials in the nanoelectronics era, resistive switching memory, metal gate work function engineering, flexible electronics, graphene band engineering.

Last modified Mon, 10 Dec, 2012 at 11:53

Title Author(s) Journal Date
Ultra-high-yield growth of vertical single-walled carbon nanotubes: Hidden roles of hydrogen and oxygen Nishi, Y, et. al. Proceedings of the National Academy of Sciences of the United States of America 11-2005
An atomic force microscope study of surface roughness of thin silicon films deposited on SiO{sub 2} Nishi, Y, et. al. IEEE Transactions on Nanotechnology 05-2005

IEEE Life Fellow (1987) IEEE Jack A. Morton Award (1995) IEEE Robert N. Noyce Medal (2002) SEMI Lifetme Achievement Award (2008), Fellow International of Japan Society of Applied Physics (2012)

NMTRI, Nonvolatile Memory Technology Research Initiative

Principal Investigators: Yoshio Nishi, Krishna Saraswat, Philip Wong, Simon Wong, Yi Cui

Vision: This initiative for non-volatile memory research aims at dealing with challenges of increasing needs for embedded memory with high density and low cost with power minimization by forming an interdisciplinary team of faculty, staff and students to look into technical feasibility at the device level, circuit/system level as well as develop a fundamental understanding for a variety of new non-volatile memory phenomena, materials and processes.

Scope: NMTRI covers areas of research (i) how barrier engineering can improve flash memory (ii) how scalable are the various resistance switch materials and mechanisms (iii) how nanowire diodes can be integrated with resistive switches in crosspoint arrays (iv) how cell and circuit innovations can improve performance and (v) how bulk and interface effects control reliability and endurance. The scope of the initiative is for 5 years aiming at possible infusion into the 32-21nm ITRS nodes and beyond.
Participating core faculty members (in alphabetical order):

• Yi Cui (MSE), ferroelectric nanowires
• Yoshio Nishi (EE and MSE), metal sulphides and oxides based resistance change memory
• Krishna Saraswat (EE and MSE), floating gate flash memory with barrier engineering
• Philip Wong (EE), phase change based resistance change memory
• Simon Wong (EE), non-volatile memory cells and circuits

Member companies:
• Hitachi
• COSAR, Korean Consortium
• Intel Corporation
NEC Electronics
• Micron Technology
• Qimonda
• Samsung Electronics
• Spansion
• SunDisk
• Texas Instruments
• Toshiba Corporation

INMP, Initiative for Nanoscale Materials and Processes

This is a continuation of the fixed term research project, INMP, based upon a limited company involvement under CIS umbrella. Some of research items under this initiative were first studied under CIS Seed Fund and also Custom Research/FMA, and further developed to a large initiative with much enhanced resources funded by industrial members who have specific interest and need for this research area.

Vision: Pursue in-depth understandings of metal gate/high K dielectrics/high mobility channel structures as the key building block of charge control devices and study materials and processes at atom/molecular levels, and investigate new innovative processes for such structures.

Scope: ITRS technology nodes of 32nm and beyond

Memberships:
Participating Faculty members are from multiple disciplines as listed below:
• Bruce Clemens (Material Science and Engineering), work function of metal bilayer and alloys
• Walter Harrison (Applied Physics), physics of solid state surfaces/interfaces
• Paul McIntyre (Material Science and Engineering), ALD of high K dielectrics on Ge and high K-Ge interfaces
• Charles Musgrave (Chemical Engineering), DFT modeling and simulations of surfaces and interfaces
• Yoshio Nishi (Electrical Engineering), work function and metal-insulator, metal-semiconductor interface characterization and engineering
• Krishna Saraswat (Electrical Engineering), Ge, SiGe MOS device structure fabrication and characterizations
• Philip Wong (Electrical Engineering), electrical characterizations of interfaces for high k-Si, Ge systems

Participating Industrial members are listed below:
• AMD
• Applied Materials
• COSAR
• IBM Corporation
• Intel Corporation
• NEC Electronics
• Taiwan Semiconductor Manufacturing Co
• Tokyo Electron Laboratories
• Toshiba Corporation

INMP Phase 2 holds bi-annual reviews as well as topical workshops in four key areas, i.e. metal gate and work function control, high K dielectrics and carrier transpo