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IEEE honors engineering alum for pioneering transistor innovations

Stanford electrical engineer and two others are credited with shrinking computer chip, enabling a new generation of computing technology.

Tahir Ghani, an Intel Fellow and longtime leader in transistor technology development, is one of three recipients of this year's IEEE Jun-ichi Nishizawa Medal recognizing his sustained leadership in developing innovative transistor technologies for advanced logic products. 

Ghani (MS 1987, PhD 1995, Electrical Engineering) was one of three winners – the others were  Mark T. Bohr and Robert S. Chau, also Intel Fellows – who the IEEE credited with important innovations that made it possible to continue shrinking chip size. The medal is awarded annually for outstanding contributions to material and device science and technology.

Ghani’s other honors include the SEMI Award for North America (2008) and the EDN Innovator of the Year Award (2008). 

According to IEEE, the honorees played key leadership roles at Intel in developing the "three biggest changes in transistor technology over the past decade."

Ghani led the integration teams for Intel’s silicon germanium strained silicon process for 90-nanometer (nm) logic chips, high-k metal gate transistors for 45-nm logic chips and tri-gate transistors featured in the 22-nm technology node.

"Each of these innovations overcame roadblocks to enable the continued shrinking of chip size, making chips that are smaller, faster and consume less energy," the IEEE said. "Their work has provided smarter, faster and more efficient devices, enabling a new generation of computing technology for applications ranging from super computers to handheld electronics."