Dally investigates methods for applying VLSI technology to solve information processing problems. His current projects include network architecture, multicomputer architecture, media-processor architecture, and high-speed (4Gb/s) CMOS signaling. His research involves demonstrating novel concepts with working systems. Previous systems include the MARS Hardware Accelerator, the Torus Routing Chip, the J-Machine, M-Machine, and the Reliable Router. His group has pioneered techniques including fast capability-based addressing, processor coupling, virtual channel flow control, wormhole routing, link-level retry, message-driven processing, and deadlock-free routing.